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Learn how to build industry standard assertions in SystemVerilog (SVA) with open-source frameworks!
3/28/20231 min read
We are excited to share our experience in porting an industry-standard Assertion IP written in SVA (SystemVerilog Assertions) to Verilator, a popular open-source simulator.
https://www.fossi-foundation.org/latchup/#presentations
SVA based Checker IP in Verilator
Checkers are a critical part of the design verification process. With the advent of constrained-random techniques, a lot of stimulus-generation capabilities are supported by languages, methodologies, and supporting tools. Ensuring that a design behaves as per the specification is achieved using various forms of checkers. The term “checker” at times means different things to different people. With SystemVerilog 2009 standard making “checker” as a keyword in the language itself, we would like to use that for temporal checks using assertions. Verilator is a free and open-source simulator that can convert SystemVerilog code into a cycle-accurate executable model. Assertions are statements that specify properties or constraints that the design should satisfy. In this paper, we present our experience in porting some of our Checker IPs (APB, AHB, etc.) developed and used in production to Verilator. Given the SVA support is still maturing in Verilator, our team had to adapt the code to be restricted to what the tool supports. We also developed unit tests to verify these properties in Verilator. We will share our findings, potential areas to improve, etc. Our intention is to make this code base available as part of GO2UVM library.