Assertions & Verilator - opensource CIP development

Assertions are critical to checking design correctness especially around protocol requirements. We at AsFigo took up the task of porting a production-ready Checker IP (CIP) written in SVA to Verilator, an open-source simulator. Below is a brief on Verilator (created by Generative AI tool, edited by us):

Verilator is a popular simulator used for testing digital hardware designs. It is an open-source software that can convert Verilog or SystemVerilog code into an executable C++ model. The simulator generates a cycle-accurate simulation of the digital hardware design, making it an effective solution for debugging and testing. One of the benefits of using Verilator simulator is its speed, as it can simulate designs at much faster rates than other simulators. Overall, Verilator simulator is a valuable resource for digital hardware designers and engineers looking to improve their design and testing processes.

So, what exactly did we achieve? Well, a few notes:

• We took APB and AHB assertions, ported them to Verilator's subset of SVA constructs.

• Ported a popular open-source Unit testing frameworks - SVUnit to run on Verilator

• Developed Unit tests for each assertion in APB, ran them with Verilator

• Raised few issues with the community to improve SVA support in this tool chain

  • We even fixed one ourselves, and raised a PR to Verilator team!

• Added all to a public GitHub repo!

AsFigo